Led full-chip logic equivalency simulations as directly responsible individual for tapeout approval. Accelerated power analysis by 8 months and eliminated 100+ slow gate-level simulations.

Built AI hardware verification agents to generate RTL testbenches for functional verification. Claimed SoTA on Nvidia's VerilogEval-Human benchmark.

Custom built a verilog package manager for LLM calls to autonomously pull RTL IP from known databases. Improved correctness of one-shot LLM generated SystemVerilog code by 27%.

Designed deep space data storage system using 5D optical storage paradigms. Worked under NASA Cubesat lead in Virginia.